(1) Field of the Invention
The present invention relates to methods of fabricating shallow trench isolation and, more particularly, to methods of fabricating shallow trench isolation filled with two or more dielectrics for isolation, coupling, or stress relief in the fabrication of integrated circuits.
(2) Description of the Prior Art
Shallow-trench isolation (STI) is the most popular isolation scheme for advanced CMOS (e.g. 0.25 um and beyond). However, as the spacing of STI is continuously scaled down to <0.15 um, there is significant field penetration into the channel (or body) area from the bias of adjacent source/drain junctions. This is discussed in “Characteristics of CMOS device isolation for the ULSI age”, A. Bryant, W. Hansch, and T. Mii, International Electron Device Meetings, p. 671, 1994, “Three-dimensional DIBL for shallow-trench isolation MOSFET's”, C. Wang, P. Zhang, IEEE Trans. on Electron Device, V. 46, No. 1, p. 139, 1999, and “The impact of isolation pitch scaling on Vth fluctuation in DRAM cell transistors due to neighboring drain/source electric field penetration”, J. H. Sim, J. K. Lee, and K. Kim, Symposium of VLSI technology, p. 32–33, 1998. Therefore, such “non-perfect” isolation from STI can result in undesirable effects, such as threshold voltage (Vt) fluctuations, with increasing impact in future technology with smaller STI spacing.
One way to eliminate such field penetration effect, a metallic-shielded STI, was proposed in “High-performance cell transistor design using metallic shield embedded shallow trench isolation (MSE-STI) for Gbit generation DRAM's”, J. H. Sim, J. K. Lee, and K. Kim, IEEE Transaction on Electron Devices, Vol. 46, No. 6, p. 1212–1217, 1999. In this proposal, a layer of conducting material (e.g. doped poly) fills the isolation trench after liner oxidation. The grounded conducting material in the trench can provide good shielding and therefore can eliminate transistor's narrow-width effect and Vt fluctuations. There is certainly continuous need for better isolation structure and process.
Interestingly, such field penetration effect due to “non-perfect” STI may also be utilized for forming vertical resistors, FETs, and circuits as disclosed in co-pending U.S. patent applications Ser. No. 10/268,585 and to the same inventor. Thus, the coupling effect through STI may also be useful if the coupling through STI is enhanced.
Furthermore, the effect of stress in the active area is discussed in “New mechanical reliability issues for deep-submicron devices”, H. Miura and S. Ikeda, Symposium of manufacturing technology workshop, Taiwan, p. 140–147, 1998. It is desired to control this stress, especially as it relates to isolation formation. Other related literature includes co-pending U.S. patent application Ser. No. 10/444,874, “Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding” by L. J. Huang et al, Symposium VLSI Tech., Dig. Tech. Papers, Kyoto, Japan, p. 57–58, 2001; “Fabrication and analysis of deep submicron strained-Si n-MOSFETs”, by K. Rim et al, IEEE Trans. Electron Dev., vol. 47, no. 7, p. 1406–1415, July 2000; “Strained Si surface channel MOSFETs for high performance CMOS technology”, by K. Rim, ISSCC, paper #7.3, p. 116–117, 2001; “Carrier mobility and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates”, by M. T. Currie et al, J. Vacuum Science Technology B, vol. 19, no. 6, p. 2268, November/December 2001; “Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial Silicon-Germanium”, by Y. C. Yeo et al, IEDM, p. 753, 2000; “SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications”, by J. D. Cressler, IEEE Trans. Microwave and Techniques, V. 46, No. 5, p. 572–589. Related patents include U.S. Pat. No. 6,297,128 to H. S. Kim et al and U.S. Pat. No. 6,037,237 to M. H. Park et al.
U.S. Pat. No. 6,074,909 to Gruening shows a STI and a vertical transistor process. U.S. Pat. No. 6,255,176B1 to Kim et al shows a STI with a high dielectric constant material. U.S. Pat. No. 6,194,283B1 to Gardner et al discloses a low dielectric constant spacer layer in a STI process. U.S. Pat. No. 5,742,091 to Hebert shows a low dielectric constant material as a liner or as a fill layer in a STI process.